This relates generally to integrated circuits, and more particularly, to integrated circuits with pulse latches.
Pulse latches are level-sensitive latches that are controlled by clock pulse signals (i.e., level-sensitive latches are enabled during certain phases of clock pulse signals). Clock pulse signals are typically generated from square wave clock signals (i.e., clock signals having a 50% duty cycle) using pulse generators. These clock pulse signals have clock pulses that are triggered by rising clock edges of the square wave clock signals.
Pulse latches can be used to implement time borrowing schemes in integrated circuits. Time borrowing schemes may allow circuit performance to be improved by optimizing timing performance along critical circuit paths.
As circuit density and clock rates increase with improvements in process technology, the amount of dynamic power consumed increases. The clocking circuitry is a substantial contributor to this power consumption. It would therefore be desirable to be able to provide pulse latch circuitry with enhanced power efficiency.